Program and Schedule

Final Program (PDF, 3MB)

Program at a Glance (PDF, 20KB)

A note to speakers: 30 minutes including 5 minutes Q&A is allocated for each presentation in Regular Sessions, Industry Session and Workshops. 10 minutes including 3 minutes Q&A is scheduled for each FA presentation.

Keynote Speech I (Sunday, November 18, 2012, 9:00-10:00)

Title: Toward Dependability of Information Society

Speaker: Dr. Takashi Nanya (Canon Inc.)


As networked computing systems pervade every aspect of the modern information society, we are increasingly faced with serious threats to dependability due to problems caused by accidental events such as human mistakes, physical malfunctions and unpredictable interactions among subsystems, and by intentional human behavior being either malicious or non-malicious. With significant increases in system complexity and rapid changes in system technologies and environments, what we need is to take a cross-layer full-system-design approach to achieving dependability of the information society that consists of multiple layers including information systems at a lower level, infrastructures at a middle level and service activities at a higher level. In this talk, we identify currently existing research gaps in the dependable computing community, discuss major challenges, and give views of future directions in research on dependability of an evolving "system of systems" toward trusted information society.


Takashi Nanya received the B.E. and M.E. degrees in Mathematical Engineering and Information Physics from the University of Tokyo, Japan, in 1969 and 1971, respectively, and his Ph.D. degree in Electrical Engineering from the Tokyo Institute of Technology, Japan in 1978. After he worked for the NEC Central Research Laboratories from 1971 to 1981, he joined the Tokyo Institute of Technology where he was an associate professor from 1981 to 1989, and a professor from 1989 to 1996. From 1996 to 2010, he was a professor of the University of Tokyo. From 2001 to 2004, he was the director of the Research Center for Advanced Science and Technology, and a councilor of the University of Tokyo. In 2010, he left the University of Tokyo and joined Canon Inc., Japan, where he is now working as a full-time adviser in research and development. In past years, he served as the Chair of IEEE-CS TC on Dependable Computing and Fault Tolerance, and the Chair of the Steering Committee of International Conference on Dependable Networks and Systems (DSN). He also served as a Vice-chair of the IFIP WG 10.4 "Dependable Computing and Fault Tolerance". He served as the General Chair of ASYNC, PRDC, DSN and ISAS, and as the PC Chair of FTCS and ASP-DAC. He served as an Associate Editor of IEEE Transactions on Computers and a Guest Editor of IEE Proceedings on Computer and Digital Techniques. He is a Fellow of the IEEE and IEICE, and a Professor Emeritus of both the University of Tokyo and the Tokyo Institute of Technology. He is a member of the Science Council of Japan.

Keynote Speech II (Monday, November 19, 2012, 13:30-14:30)

Title: Test and DfT as Enablers for Dependable 3D Integrated Circuits

Speaker: Prof. Krishnendu Chakrabarty (Duke University)


Despite the numerous benefits offered by 3D integration, testing remains a major obstacle that hinders its widespread adoption. Test techniques and design-for-testability (DfT) solutions for 3D ICs have remained largely unexplored in the research community, even though experts in industry have identified a number of hard problems related to the lack of probe access for wafers, test access to modules in stacked wafers/dies, thermal concerns, and new defects arising from unique processing steps. In this talk, the speaker will present a number of testing and DfT challenges, and describe some of the solutions being advocated for these challenges. The presentation will focus on the following hot topics:


Krishnendu Chakrabarty received the B. Tech. degree from the Indian Institute of Technology, Kharagpur, in 1990, and the M.S.E. and Ph.D. degrees from the University of Michigan, Ann Arbor, in 1992 and 1995, respectively. He is now Professor of Electrical and Computer Engineering at Duke University. Prof. Chakrabarty is a recipient of the National Science Foundation Early Faculty (CAREER) award, the Office of Naval Research Young Investigator award, the Humboldt Research Fellowship from the Alexander von Humboldt Foundation, Germany, and several best papers awards at IEEE conferences.

Prof. Chakrabarty's current research projects include: testing and design-for-testability of integrated circuits; digital microfluidics, biochips, and cyberphysical systems; optimization of enterprise systems. He has authored 12 books on these topics, published over 420 papers in journals and refereed conference proceedings, and given over 185 invited, keynote, and plenary talks. Prof. Chakrabarty is a Fellow of IEEE, a Golden Core Member of the IEEE Computer Society, and a Distinguished Engineer of ACM. He was a 2009 Invitational Fellow of the Japan Society for the Promotion of Science (JSPS). He served as a Distinguished Visitor of the IEEE Computer Society during 2005-2007, and as a Distinguished Lecturer of the IEEE Circuits and Systems Society during 2006-2007. Currently he serves as an ACM Distinguished Speaker, a Distinguished Visitor of the IEEE Computer Society for 2010-2012, and a Distinguished Lecturer of the IEEE Circuits and Systems Society (2012-2013).

Prof. Chakrabarty is the Editor-in-Chief of IEEE Design & Test of Computers and ACM Journal on Emerging Technologies in Computing Systems. He is also an Associate Editor of IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on Circuits and Systems II, and IEEE Transactions on Biomedical Circuits and Systems. He serves as an Editor of the Journal of Electronic Testing: Theory and Applications (JETTA).

Embedded Tutorial (Sunday, November 18, 2012, 17:00-18:00)

Title: Highly Reliable Signal Processing Technologies for Dependable Solid-State Drives (SSDs)

Speaker: Prof. Ken Takeuchi (Chuo University)


Solid-State Drives which use flash memories have enabled innovations in various nano-scale VLSI memory systems for personal computers, smart phones and enterprise servers. However, as memory cells are scaled down, the reliability of memory cells significantly degrades because of reduced electrons and interferences with neighboring cells. This tutorial provides a comprehensive review on high reliable signal processing technologies such as ECCs for the dependable SSDs.


Ken Takeuchi is currently a Professor at the Department of Electrical, Electronic, and Communication Engineering of Chuo University. He is now working on the VLSI circuit design, signal processing and device especially on the emerging non-volatile memories, 3D-integrated SSDs and low-power 3D-LSI circuits. He was an Associate Professor at the University of Tokyo from 2007 till 2012. From 1993 till 2007, he had been leading Toshiba's NAND flash memory circuit design team and commercialized six world's highest density flash memory products. He holds 210 patents worldwide.